/****************************************************************************
 ****************************************************************************
 ***
 ***   This header was automatically generated from a Linux kernel header
 ***   of the same name, to make information necessary for userspace to
 ***   call into the kernel available to libc.  It contains only constants,
 ***   structures, and macros generated from the original header, and thus,
 ***   contains no copyrightable information.
 ***
 ***   To edit the content of this header, modify the corresponding
 ***   source file (e.g. under external/kernel-headers/original/) then
 ***   run bionic/libc/kernel/tools/update_all.py
 ***
 ***   Any manual change here will be lost the next time this script will
 ***   be run. You've been warned!
 ***
 ****************************************************************************
 ****************************************************************************/
#ifndef _ASM_WAR_H
#define _ASM_WAR_H
#include <war.h>
#define R4000_WAR 0
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define R4400_WAR 0
#define DADDI_WAR 0
#ifndef R4600_V1_INDEX_ICACHEOP_WAR
#error Check setting of R4600_V1_INDEX_ICACHEOP_WAR for your platform
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#endif
#ifndef R4600_V1_HIT_CACHEOP_WAR
#error Check setting of R4600_V1_HIT_CACHEOP_WAR for your platform
#endif
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#ifndef R4600_V2_HIT_CACHEOP_WAR
#error Check setting of R4600_V2_HIT_CACHEOP_WAR for your platform
#endif
#ifndef R5432_CP0_INTERRUPT_WAR
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#error Check setting of R5432_CP0_INTERRUPT_WAR for your platform
#endif
#ifndef BCM1250_M3_WAR
#error Check setting of BCM1250_M3_WAR for your platform
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#endif
#ifndef SIBYTE_1956_WAR
#error Check setting of SIBYTE_1956_WAR for your platform
#endif
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#ifndef MIPS4K_ICACHE_REFILL_WAR
#error Check setting of MIPS4K_ICACHE_REFILL_WAR for your platform
#endif
#ifndef MIPS_CACHE_SYNC_WAR
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#error Check setting of MIPS_CACHE_SYNC_WAR for your platform
#endif
#ifndef TX49XX_ICACHE_INDEX_INV_WAR
#error Check setting of TX49XX_ICACHE_INDEX_INV_WAR for your platform
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#endif
#ifndef RM9000_CDEX_SMP_WAR
#error Check setting of RM9000_CDEX_SMP_WAR for your platform
#endif
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#ifndef ICACHE_REFILLS_WORKAROUND_WAR
#error Check setting of ICACHE_REFILLS_WORKAROUND_WAR for your platform
#endif
#ifndef R10000_LLSC_WAR
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#error Check setting of R10000_LLSC_WAR for your platform
#endif
#ifndef MIPS34K_MISSED_ITLB_WAR
#error Check setting of MIPS34K_MISSED_ITLB_WAR for your platform
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#endif
#endif
